The research team of the AnalogMIC lab has more than ten-year experience in the design of Analog integrated circuits in CMOS and BiCMOS technologies.


The main research topics are:

- Mixed-signal Memory Accelerators for Deep Neural Network: full memory design, compute cell (SRAM or RRAM based), and I/O interfaces (D/A and A/D converters)

- Design of Analog-to-Digital Converters (ADCs), considering the power-speed-resolution trade-off:  Sigma-Delta ADCs for high-resolution and low-speed, low-power SAR ADCs, and pipeline or flash converter for high bandwidth and sampling frequency.

-Ultra-low power analog blocks: amplifiers, bandgap references, low-dropout regulators, and programmable voltage reference circuits.

-RF circuits for low-power radios, RFID tags, and energy harvesting

-Embedded systems and wireless sensors for precision agriculture

-CMOS circuits for automotive applications


The current research activity focuses on:

-accelerators with Analog in-Memory computing for Deep Neural Networks with advanced memory devices

-Low-power circuits for implantable medical devices

-Wireless Biosensor Node for in-vivo plant monitoring

Recent Research Projects

2022-2025: National Recovery and Resilience Plan (NRRP), Mission 04 Component 2 Investment 1.5 - NextGenerationEU, Call for tender n. 3277 dated 30/12/2021, Award Number:  0001052

2022-2024: “Innovative Integrated Circuits for Smart Sensors”, – Programma Operativo (PON) “Ricerca e Innovazione”

2014-2020- Azioni IV.4 –“Dottorati e contratti di ricerca su tematiche dell’innovazione”  

2013-2019: Collaboration Research Agreement with STMicroelectronics, Agrate, Italy

2019-2022: Research Contract with STMicroelectronics on Low-Power Radio Receiver design.

2016-2022: Research Cooperation with imec – Netherlands on low-power circuits for implantable devices.

Selected publications

1.    A. Boni, F. Malena, F. Saccani, M. Amoretti, and M. Caselli, “Boosting RRAM-based Mixed-Signal Accelerators in FD-SOI technology for ML applications,” IEEE Journal of Exploratory Solid-State Computational Devices and Circuits, 2023.

2.    M. Caselli, P. Debacker, and A. Boni, “Memory Devices and A/D Interfaces: Design Trade-offs in Mixed-Signal Accelerators for Machine Learning Applications,” IEEE Transactions on Circuits and Systems II Express Briefs, 2022.

3.    F. Malena, A. Boni, and M. Caselli, “A PWM-DAC for Analog In-Memory Computing in Mixed-Signal Accelerators,” in IEEE PRIME 2023 - 18th International Conference on Ph.D Research in Microelectronics and Electronics, Proceedings, 2023, pp. 273–276.

4.    M. Ronchi et al., “An Integrated Low-power 802.11ba Wake-up Radio for IoT with Embedded Microprocessor,” in 2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

5.    M. Caselli, E. Tiurin, S. Stanzione, and A. Boni, “An Ultra Low-Power Programmable Voltage Reference for Power-Constrained Electronic Systems,” IEEE Transactions on Circuits and Systems I Regular Paper, vol. 70, no. 2, pp. 618–630, 2023.

6.    M. Caselli, B. Lukita, A. Boni, and S. Stanzione, “A Low-Power Sample-and-Hold Programmable Voltage Reference Based on Ripple Monitoring,” in Proceedings - IEEE International Symposium on Circuits and Systems, 2023, vol. 2023-May.

7.    M. Caselli et al., “A Wireless Biosensor for in-Vivo and Real-Time Plant Monitoring for Smart Agriculture,” in 2023 IEEE Conference on AgriFood Electronics (CAFE), 2023, pp. 162–166.

8.    A. Boni, M. Caselli, A. Magnanini, and M. Tonelli, “CMOS Interface Circuits for High-Voltage Automotive Signals,” Electronics , vol. 11, no. 6. 2022, doi: 10.3390/electronics11060971.

9.    M. Caselli, S. Subhechha, P. Debacker, A. Mallik, D. Verkest,“Write-Verify Scheme for IGZO DRAM in Analog in-Memory Computing,”- IEEE International Symposium on Circuits and Systems, Austin TX, 2022, accepted

10.    M. Caselli, D. Bhattarcharjee, A. Mallik, P. Debacker, D. Verkest, “Tiny ci-SAR A/D Converter for Deep Neural Networks in Analog in-Memory Computation,” IEEE International Symposium on Circuits and Systems, Austin
TX, 2022, accepted

11.    A. Boni, L. Giuffredi, G. Pietrini, M. Ronchi, and M. Caselli, “A Low-Power Sigma-Delta Modulator for Healthcare and Medical Diagnostic Applications,” IEEE Trans. Circuits Syst. I Regul. Pap., vol. 69, no. 1, pp. 1–13, 2022,
doi: 10.1109/TCSI.2021.3112342.

12.    N. Laubeuf, J. Doevenspeck, I. A. Papistas, M. Caselli, S. Cosemans, P. Vrancx, D. Bhattacharjee, A. Mallik, P. Debacker, D. Verkest, F. Catthoor, R. Lawereins, “Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration,” ACM Transactions on Design Automation of Electronic Systems, 2022-Feb, doi:10.1145/3498328

13.    M. Caselli, I. A. Papistas, S. Cosemans, A. Mallik, P. Debacker, D. Verkest “Charge Sharing and Charge Injection A/D Converters for Analog In-Memory Computing”, 2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) – Paper selected for extended version on Transactions on Circuit and Systems 1

14.    M. Caselli, C. van Liempd, A. Boni, and S. Stanzione, “A low-power native NMOS-based bandgap reference operating from −55°C to 125°C with Li-Ion battery compatibility,” Int. J. Circuit Theory Appl., vol. 49, no. 5, pp. 1327–1346, 2021, doi: 10.1002/cta.2986.

15.    M. Caselli, M. Ronchi, and A. Boni, “Power management circuits for low-power RF energy harvesters,” J. Low Power Electron. Appl., vol. 10, no. 3, pp. 1–16, 2020, doi: 10.3390/jlpea10030029.

16.    M. Caselli, M. Tonelli, and A. Boni, “Analysis and Design of an Integrated RF Energy Harvester for Ultra Low-Power Environments,” Int. J. Circuit Theory Appl., vol. 47, pp. 1086–1104, 2019, doi: 10.1002/cta.2637.

17.    N. Adorni, S. Stanzione, and A. Boni, “A 10-mA LDO with 16-nA IQ and Operating from 800-mV Supply,” IEEE J. Solid-State Circuits, vol. 55, no. 2, pp. 404–413, 2020, doi: 10.1109/JSSC.2019.2948820.

18.    A. Boni, M. Tonelli, A. Magnanini, and M. Caselli, “Fully integrated CMOS overvoltage protection circuit for automotive applications,” Electron. Lett., vol. 51, no. 17, pp. 1316–1318, 2015, doi: 10.1049/el.2015.1813.

19.    A. Boni, “Op-amps and startup circuits for CMOS bandgap references with near 1-V supply,” IEEE J. Solid-State Circuits, vol. 37, no. 10, pp. 1339–1343, 2002, doi: 10.1109/JSSC.2002.803055.

20.    A. Boni, A. Pierazzi, and D. Vecchi, “LVDS I/O interface for Gb/s-per-pin operation in 0.35-μm CMOS,” IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 706–711, 2001, doi: 10.1109/4.913751.

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